This invention relates generally to buffer circuitry for high frequency applications, and more particularly the invention relates to a high frequency input buffer operable with low power voltages.
In modulator circuitry for cellular phone applications, in phase (I, I) and quadrature phase (Q, Q) inputs are received by respective differential buffers. FIG. 1 is a schematic of a conventional buffer for the baseband I, I inputs using a Vcc power source of 5 V, for example. The bipolar transistors Q1, Q2 form a differential pair which respectively receive the I and I inputs through resistors R1, R3. Resistor R2 connected between the transistor base regions forms a voltage divider with R1 and R2. Vcc is connected through resistors R7, R8 to the collectors of Q1, Q2 with the buffer outputs taken at the collectors. Transistors Q3, Q4 form a current source for the differential pair with diode connected transistor Q4 connected through resistor R6 to a regulated voltage (Vreg) and to circuit ground with the base of Q4 providing base current to Q3. Transistor Q3 is connected to circuit ground and through resistors R4, R5 to the emitters of Q1, Q2.
Since Vce of Q3 has a minimum voltage of 0.6 V for gallium arsenide heterojunction bipolar transistor (GaAs HBT) technology, and 0.8 to 1.0 V for silicon bipolar technology, the bases of Q1 and Q2 must be at 2 V or above. Therefore, Vcc must be greater than 4 V if the I and Q ports are at Vcc/2. If Vcc is less than 4 V, then the current source cannot be implemented and a common resistor to ground must be used. Further, a power down function cannot be implemented. If Vcc is further reduced to 3 V and less, Vcc/2 becomes less than Vbe of the heterojunction bipolar transistor and the circuit cannot be implemented at all with HBT technology.